Join the talk of the chief architect of the Andes, Dr Thang Tran, “Demystifying the RISC-V vector extension”

Santa Clara, July 09, 2021 (GLOBE NEWSWIRE) –

What: Andes Technology Corp. will hold an online zoom conference. The hour-long event will be the first in a 4-part lecture series on the design of next-generation vector processors. It will feature a 5-step pipeline and 8-step superscalar vector processor in order based on the latest AndeStar â„¢ V5 architecture from Andes. Both have won design awards from major TSMC foundry customers.

who: Dr. Thang Tran, Senior Architect and High Performance Computing (HPC) Veteran at Andes Technology Corp. will be the presenter of the series. Dr Tran is an industry expert in HPC development. He architectured and designed the Andes RISC-V out-of-order (OOO) vector processor (VLEN / SIMD = 512b) in 9 months using a revolutionary algorithm that is unlike any previous known OOO superscalar design that did not temporary registers (not rename, not reorganize the buffer).

Why: Dr. Trang’s lecture will illustrate the most important feature of this vector processor: its simplicity. The vector processor issues 8 micro-operations per cycle with up to 14 vector instructions in parallel execution.

Who should be present: architects, designers and developers of SoC and ASIC software.

When: Tuesday July 13, 2021 at 9:00 a.m. Pacific Daylight Time.

Or: To attend the conference, register on
Hope to see you there.

CONTACT: Jonah McLeod 510 449 8634

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